This application claims the priority benefit of Taiwan application serial No. 88117936, filed Oct. 16, 1999.
1. Field of the Invention
This invention relates to computer technology, and more particularly, to a method of adjusting an access sequencing scheme for a number of PCI (Peripheral Component Interconnect) compliant units coupled to a PCI bus system on a computer system.
2. Description of Related Art
FIG. 1 is a schematic diagram showing the architecture of a computer system with a PCI bus system. As shown, the computer system includes a CPU 10 and a primary memory unit 11, and is coupled via a host bridge 12 (which is also called North Bridge, NB) to a PCI bus system 14 which is further coupled to a number of PCI-compliant units, such as a graphics adapter 16a, an expansion-bus bridge 16b, a LAN adapter 16c, and a SCSI host bus adapter 16d. Each of these adapters can issue a request (RQ) to use the PCI bus system 14 when transaction over the PCI bus system 14 is intended. The request signal is first sent to the host bridge 12 for arbitration. When the request is granted, the host bridge 12 returns a grant signal (GNT) to grant the use of the PCI bus system 14 by the request-issuing adapter.
The data communication between the host bridge 12 and the PCI-compliant units 16a, 16b, 16c, 16d over the PCI bus system 14 is achieved through the use of a set of control signals, including FRAME (cycle frame), AD, (address), CBE (command/byte enable), IRDY (initiator ready), TRDY (target ready), and STOP (stop). Throughout this specification, the term xe2x80x9cinitiatorxe2x80x9d refers to the unit that initiates a request to use the PCI bus system 14, which can be either the host bridge 12 or any one of the PCI-compliant units 16a, 16b, 16c, 16d, while the term xe2x80x9ctargetxe2x80x9d refers to the unit that the initiator intends to transfer data thereto.
The FRAME signal is issued by the initiator to indicate the starting time and the duration of the intended data communication over the PCI bus system 14. When the FRAME signal is set to LOW state, it enables the initiator to gain access to the PCI bus system 14. During the address phase, the initiator issues the AD signal indicative of the valid address and the CBE signal (CBE[3:0] for enabling the command/byte transfer. The CBE signal is composed of 4 bits which can represent 16 different commands. The CBE signal format is fully described in the PCI standard, so description thereof will not be further detailed. Subsequently, during the data phase, the initiator sends out the AD signal representative of the data to be transferred over the PCI bus system 14 to the target. When the FRAME signal is disabled, it indicates that the transaction is completed. When the initiator is ready to send out data, the IRDY signal is enabled; and when the target is ready to receive the data, the TRDY signal is enabled. During a read operation, the enabling of the IRDY signal indicates that the initiator is ready to receive data from the target; whereas during a write operation, the enabling of the TRDY signal indicates that the target is ready to receive data. When the target wants to stop the transaction, it issues the STOP signal to the initiator.
FIG. 2 is a signal diagram showing the waveforms and timings of the above-mentioned signals specified by the PCI standard for an initiator to perform a read operation on a target. In this signal diagram, the duration indicated by the reference numeral 20 is called a bus transaction period, during which the data exchange is carried out. The bus transaction period 20 includes an address phase 22 and a number of data phases 24a, 24b, 24c. The data phases 24a, 24b, 24c each include a wait cycle, respectively designated by the reference numerals 26a, 26b, 26c, and a data transfer cycle, respectively designated by the reference numerals 28a, 28b, 28c. 
The PCI bus system is docked by a system clock signal CLK. During the first period T1 of CLK, the initiator issues a FRAME signal to indicate that it intends to transfer, data to a certain target. Subsequently, the initiator sends out the AD signal indicative of the start address specifying the target where the initiator intends to read data. After this, the initiator sends out the CBE signal. The CBE signal is in the enabled state during all the data phases 24a, 24b, 24c. During the next period T2, the initiator issues the IRDY signal indicating that it is ready for data communication. However, since this period is the wait cycle 26a in the data phase 24a, the target is still unready. During the next period T3, the target is ready and hence issues the TRDY signal indicative of this condition. This causes the target to transfer data to the initiator during the data transfer cycle 28a. During the next period T4, the target disables the TRDY signal, indicating that the transfer of the current piece of data is complete, and then prepares the next piece of data for transfer. This is the wait cycle 26b of the data phase 24b. During the next period T5, the target enables the TRDY signal again, indicating that it is ready to transfer data, When the IRDY signal is also enabled during the data transfer cycle 28b, the initiator starts to read data from the target. During the next period T6, the initiator disables the IRDY signal to indicate that it is unable to receive any more data. However, since the TRDY signal is still in enabled state, the wait cycle 26c is activated by the initiator. During the next period T7, the initiator is again ready to receive data and hence enables the IRDY signal. When the TRDY signal is also enabled during the data transfer cycle 28c, the initiator starts to read data from the target. This completes the read operation.
FIG. 3 is a signal diagram showing the waveforms and timings of various signals specified by the PCI standard for a PCI-compliant unit to request the use of the PCI bus system. As shown, when any of the PCI-compliant units 16a, 16b, 16c, 16d (called the initiator) wants to transfer data over the PCI bus system 14, it issues a request signals RQ during T2. In response, the host bridge 12 issues the GNT signal at T6. This causes the initiator to put the FRAME signal at the LOW state at T7, thus enabling the initiator to use the PCI bus system for data transfer over the PCI bus system.
FIG. 4 is a schematic diagram used to depict a two-layer access sequencing scheme used by the PCI bus system for a number of PCI-compliant units coupled thereto. As shovel, the PCI bus system 14 is coupled between a CPU 10 and a plurality of PCI-compliant expansion slots on which a plurality of peripheral devices can be mounted (each expansion slot and the mounted peripheral device are collectively represented by a single box in FIG. 4 designated by the reference numerals 32, 34, 36, 38, 40). These PCI-compliant units 32, 34, 36, 38, 40 respectively utilize the request signals RQ0, RQ1, RQ2, RQ3, and RQ4 to request the use of the PCI bus system 14. The two-layer access sequencing scheme specifies a sequence loop that the PCI-compliant units 32, 34, 36, 38, 40 are allowed to gain access to the PCI bus system 14.
The two-layer access sequencing scheme includes a first-layer access sequences loop and a second-layer access sequence loop, with the first layer having a higher priority over the second layer. The first-layer access sequence loop is as follows:
CPUxe2x86x92SBxe2x86x92PCIxe2x86x92CPU
The CPU 50 is represented that the CPU access via the host bridge 12 to the PCI bus system 14. The SB 30 is represented that the South Bridge access PCI bus system 14. These PCI-compliant units 32, 34, 36, 38, 40 respectively utilize the request signals RQ0, RQ1, RQ2, RQ3, and RQ4 to request the use of the PCI bus system 14 when transaction over the PCI bus system 14 is intended. The access sequence for these request signals RQ0, RQ1, RQ2, RQ3, and RQ4 is specified by the second-layer access sequence loop as follows:
RQ0xe2x86x92RQ1xe2x86x92RQ2xe2x86x92RQ3xe2x86x92RQ4xe2x86x92RQ0.
One drawback to the forgoing two-layer access sequencing scheme, however, is that it is fixed and thus not adjustable, i.e., each PCI-compliant expansion slot is assigned to a fixed one of the request signals RQ0, RQ1, RQ2, RQ3, and RQ4. For this sake, if a low-priority PCI-compliant expansion slot is installed with a video/audio-based peripheral device, which typically transfers data in very great volumes, the data transfer over the PCI bus system would be considerably low in speed.
It is therefore an objective of this invention to provide an access sequence adjusting method that allows the user to adjust the access sequence for the PCI-compliant units coupled to the PCI bus system when a certain PCI-compliant Unit, such as a video/audio-based peripheral device, needs a high-priority to transfer a high volume of data.
In accordance with the foregoing and other objectives, the invention proposes a method of adjusting an access sequencing scheme for a number of PCI-compliant units coupled to a PCI bus system on a computer system.
When implemented on a PC, the access sequencing scheme can be adjusted by using the BIOS of the PC to set user-specified values to a special register set. The access sequencing scheme includes a first-layer access sequence loop and a second-layer access sequence loop, with the first-layer access sequence loop having a higher priority over the second-layer access sequence loop.
If a PCI-compliant unit coupled to the PCI bus system transfers data in great volumes, such as a video/audio-based peripheral device but it is associated with a request signal assigned to the second-layer access sequence loop, the invention allows the user to change the request signal to the first-layer access sequence loop to allow the video/audio-based peripheral device to have a higher priority level so that the video/audio-based peripheral device always has priority over others to use the PCI bus system. Moreover, the first-layer access sequence loop includes a number of options to provide various priority levels for the request signal being included therein, selection of which option is determined by the first register. This allows the user to assign a high priority level to any PCI-compliant unit being installed on the PC so as to allow the PCI-compliant unit to use the PCI bus system for an extended period of time. Therefore, a video/audio-based peripheral device can always be assigned the highest priority level to use the PCI bus system for transfer great volumes of video/audio data.